Treffer: Python-based DSL for generating Verilog model of Synchronous Digital Circuits

Title:
Python-based DSL for generating Verilog model of Synchronous Digital Circuits
Authors:
Datar, Mandar, Hegde, Dhruva S., Prasad, Vendra Durga, Prajapati, Manish, Manikanta, Neralla, Gupta, Devansh, Pavanija, Janampalli, Pare, Pratyush, Akash, Gupta, Shivam, Patkar, Sachin B.
Publisher Information:
2024-06-13
Document Type:
E-Ressource Electronic Resource
Index Terms:
Computer Science - Hardware Architecture, text
URL:
http://arxiv.org/abs/2406.09208
Availability:
Open access content. Open access content
Other Numbers:
COO oai:arXiv.org:2406.09208
1504841375
Contributing Source:
CORNELL UNIV
From OAIster®, provided by the OCLC Cooperative.
Accession Number:
edsoai.on1504841375
Database:
OAIster

Weitere Informationen

We have designed a Python-based Domain Specific Language (DSL) for modeling synchronous digital circuits. In this DSL, hardware is modeled as a collection of transactions -- running in series, parallel, and loops. When the model is executed by a Python interpreter, synthesizable and behavioural Verilog is generated as output, which can be integrated with other RTL designs or directly used for FPGA and ASIC flows. In this paper, we describe - 1) the language (DSL), which allows users to express computation in series/parallel/loop constructs, with explicit cycle boundaries, 2) the internals of a simple Python implementation to produce synthesizable Verilog, and 3) several design examples and case studies for applications in post-quantum cryptography, stereo-vision, digital signal processing and optimization techniques. In the end, we list ideas to extend this framework.
Comment: 9 pages, 13 figures