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Treffer: Hardware design based on Verilog HDL

Title:
Hardware design based on Verilog HDL
Authors:
Pace, Gordon J.
Publisher Information:
University of Oxford
Oxford University Computing Laboratory
Publication Year:
1998
Collection:
University of Malta: OAR@UM / L-Università ta' Malta
Subject Terms:
Calculus -- Computer programs, Verilog (Computer hardware description language), Computer hardware description languages, Deontic logic, Computer programs -- Verification
Document Type:
Dissertation doctoral or postdoctoral thesis
Language:
English
Relation:
Pace, G. J. (1998). Hardware design based on Verilog HDL (Doctoral thesis). University of Oxford.; https://www.um.edu.mt/library/oar//handle/123456789/27858
Availability:
https://www.um.edu.mt/library/oar//handle/123456789/27858
Rights:
info:eu-repo/semantics/restrictedAccess ; The copyright of this work belongs to the author(s)/publisher. The rights of this work are as defined by the appropriate Copyright Legislation or as modified by any successive legislation. Users may access this work and can make use of the information contained in accordance with the Copyright Legislation provided that the author must be properly acknowledged. Further distribution or reproduction in any format is prohibited without the prior permission of the copyright holder.
Accession Number:
edsbas.85B8D53
Database:
BASE

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Up to a few years ago, the approaches taken to check whether a hardware com- ponent works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empiri- cally) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal verification. This thesis proposes a unified approach to hardware design in which both simulation and formal verification can co-exist. Relational Duration Calculus (an extension of Duration Calculus) is devel- oped and used to define the formal semantics of Verilog HDL (a standard indus- try hardware description language). Relational Duration Calculus is a temporal logic which can deal with certain issues raised by the behaviour of typical hard- ware description languages and which are hard to describe in a pure temporal logic. These semantics are then used to unify the simulation of Verilog pro- grams, formal verification and the use of algebraic laws during the design stage. A simple operational semantics based on the simulation cycle is shown to be isomorphic to the denotational semantics. A number of laws which programs satisfy are also given, and can be used for the comparison of syntactically dif- ferent programs. The thesis also presents a number of other results. The use of a temporal logic to specify the semantics of the language makes the development of pro- grams which satisfy real-time properties relatively easy. This is shown in a case study. The fuzzy boundary in interpreting Verilog programs as either hardware or software is also exploited by developing a compilation procedure to translate programs into hardware. Hence, the two extreme interpretations of hardware description languages as software, with sequential composition as the topmost operator (as in simulation), and as hardware with parallel composition as the topmost operator are exposed. The results achieved are not limited to Verilog. The approach taken was carefully chosen so as to ...