Treffer: Final Project - Instruction Pipeline Simulation

This simulated pipeline is a simple model of an architecture that probably doesn't have much use in real applications. However, the idea of how a pipeline works and the complexity involved in designing an instruction pipeline was realized from this exercise. I tried to encompass all possible pipeline caveats into the three test programs. However, the program functionality was not completely tested for run time errors. I believe the purpose of this assignment was to evaluate the complexities of an instruction pipeline. The Appendixes A, B and C hold the test programs and their pipelines. Appendix D holds the main logic code for the pipelines. It may be a bit jumbled. This is due to the lack of knowledge that I have in programming, but I believe it is followable. The reader should be mainly concerned with the modules "readthru4" and "readthru5". This is the main logic for a 4 stage and a 5 stage instruction pipeline. I deviated a bit from my final proposal of this project. I originally planned on having a variable clock value for each stage. I chose not to do this based on time. When I had first conceived the work involved in this project, I didn't intend on it taking the time that it did. Another change from my proposal was the stages that were available. To me, a 4 and a 5 stage pipeline seemed to make more sense than a 1, 2, or 3 stage pipeline. This is why I decided to do a 4 and 5 stage pipeline. In the table section of the program, you will notice a "tblProg1", "tblProg2", "tblProg3", and "tblProgram" tables. The simulation looks at the "tblProgram" table as its table to enter in code (or change code). the other three programs refer to the test programs 1, 2 and 3 respectively.